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15.1.2.4 Modulo (Bk-c) Reduction In the case where m Bk 2 c for some small c the modulo m reduction can be performed with Algorithm 8.13. The corresponding cell is shown in Figure 15.7a: z is assumed to be a q-digit number and c a t-digit one. The value of new_z is smaller than the initial value z. After several steps, a number last_z is obtained with the following properties: last_z mod m x mod m, and last_z , Bn. If m ! Bn21, then x mod m last_z 2 q.m for some q , B. The total cost and computation time depend on the number of steps, that is, on the particular values of x and m. An additional one-step divider is necessary in order to generate the nal result (Figure 15.7b). Example 15.4 (Complete VHDL source code available.) Generate the VHDL model of a circuit that computes x modulo 2n 2 c, x being a 2.n-bit number (e.g., the result of multiplying two n-bit numbers). The structure of the data path is shown in Figure 15.8.

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The next block of logic is to detect a preamble. Figure 7.11 shows the scaling of the reference width by 2.5 and performing of the frame synchronization. Note in the implementation of Figure 7.11 that the factor of 2.5 was optimally implemented by a simple shift and add of the original signal. Similarly, we need to determine if the pulse width is indicating a bit-0 or a bit-1 (assuming the pulse width is not indicating a preamble). In the circuit shown in Figure 7.12, the data that is shifted into the framecapture shift register is dependent on the width of the current pulse. In other words, if the current pulse width is less than 1.5 the pulse width of the value of a single bit width, the data shifted in is a logic-1. Otherwise, the data is a logic-0. Finally, a transition on the output load is detected (dependent on the bit counter), the channel is selected, and the frame data is loaded into the appropriate output register as shown in Figure 7.13.

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entity data_path is port ( x: in std_logic_vector(2*n-1 downto 0); clk, sel, enable: in std_logic; z: out std_logic_vector(n-1 downto 0); equal_zero: out std_logic ); end data_path; architecture circuit of data_path is signal next_x1, next_x0, x1, x0, y1, y0: std_logic_vector(n-1 downto 0); signal x1_by_c, long_x0, y: std_logic_vector(2*n-1 downto 0); signal long_y0, minus_m, y0_minus_m: std_logic_vector(n downto 0);

When resynchronizing a signal with an encoding such as BMC, there is no choice but to sample this signal at the front end and map it into the local clock domain. No processing can take place until this initial resynchronization occurs. Additionally, the system clock that is used to sample the SPDIF stream must be suf ciently faster than the minimum pulse width of the SPDIF stream itself to provide

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x(2.n 1 .. n) x(n 1 .. 0)

enough resolution when detecting thresholds in the pulse width. Speci cally, under all relative phases of the sampling clock to the SPDIF stream, we require the following:

By working through how you feel about each of these questions, you will get a better idea about your ultimate target. This is a critical first step whether you are designing a plan from scratch or looking to amend an existing plan. With changes to all parts of the adequacy question from social security changes to demographics and employment, correct solutions arrived at 10 or 20 years ago may not work for your company today.

Figure 15.8 Data path of the modulo (2n 2 c) reduction circuit. begin with sel select next_x1<=y1 when 0 , x(2*n-1 downto n) when others; with sel select next_x0<=y0 when 0 , x(n-1 downto 0) when others; process(clk) begin if clk event and clk= 1 then if enable= 1 then x1<=next_x1; x0<=next_x0; end if; end if;

The pulse width of a logic-0 is between 1.5 and 3 of the minimum pulse width (logic-1). The pulse width of a preamble violation is between 2.5 and 4 of the minimum pulse width. There are at least two clock periods of margin in the thresholds to account for jitter of either the input stream or the system clock.

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